1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a non-volatile semiconductor memory device having memory cells each comprising volatile memory means (such as a DRAM cell) and nonvolatile memory means (such as an EEPROM cell).
2. Description of the Prior Art
A nonvolatile semiconductor memory comprises memory cells each arranged in a matrix form. Each of the memory cells has a combination of a DRAM cell MC.sub.3 and an EEPROM cell MC.sub.4 as shown in FIG. 7 (for example, Y. Terada et al, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 23, No. 1, Feb., 1988). Hereinafter, such a nonvolatile semiconductor memory device is referred to as "an NVDRAM". In FIG. 7, C.sub.2 is a DRAM capacitor, B is a bit line, CG is a control gate line, and W.sub.1 and W.sub.2 are first and second word lines, respectively. In the NVDRAM of FIG. 7, data is transferred between the DRAM cell MC.sub.3 and C.sub.2 and a external device through the bit line B. The EEPROM cell MC.sub.4 is activated only when data in the DRAM cell MC.sub.3 and C.sub.2 is transferred to the EEPROM cell MC.sub.4 ("store operation") or when data stored in the EEPROM cell MC.sub.4 is transferred to the DRAM cell MC.sub.3 and C.sub.2 ("recall operation"). Once the data of the DRAM cell MC.sub.3 and C.sub.2 is stored in the EEPROM cell MC.sub.4, the EEPROM cell MC.sub.4 retains the data stored therein, even when the power supply to the NVDRAM is turned off. This enables the data retained in the EEPROM cell MC.sub.4 to be recalled to the DRAM cell MC.sub.3 and C.sub.2 when the power is turned on again.
In the NVDRAM, the selfrefresh and selfrecall operations must be performed at a predetermined time interval, respectively. The timings of the selfrefresh and selfrecall operations are controlled by the output of an internal timer circuit, in the same manner as the selfrefresh operation in a pseudo SRAM. In order to reduce the current level for the selfrefresh operation, such an internal timer circuit is generally designed so that the output has a predetermined constant long cycle, thereby enabling the battery backup.
FIG. 6 illustrates an internal timer circuit used in a conventional NVDRAM. The internal timer circuit of FIG. 6 comprises an oscillator 61, and a plurality of 1/2 frequency dividers 62.sub.l -62.sub.n which are connected in series. The output of the oscillator 61 (frequency: f.sub.s) is coupled to the input of the first 1/2 frequency divider 62.sub.l. The last 1/2 frequency divider 62.sub.n outputs a signal of a long cycle (frequency: f.sub.s /2.sup.n). which is in turn supplied as an operation activation signal for the selfrefresh and selfrecall operations.
However, in a prior art NVDRAM, when the selfrefresh operation is performed before the store operation using the long-cycle timer output, a current leaks from the DRAM cell MC.sub.3 and C.sub.2 to cause a drop in the potential of the DRAM cell MC.sub.3. This often results in that data cannot be correctly stored into the EEPROM cell MC.sub.4. Furthermore, the use of the long-cycle timer output in the selfrecall operation required a prolonged period of time for performing the selfrecall operation.